Course Detail
Course Description
| Course | Code | Semester | T+P (Hour) | Credit | ECTS |
|---|---|---|---|---|---|
| EMBEDDED SYSTEMS | - | Spring Semester | 3+2 | 4 | 8 |
| Course Program |
| Prerequisites Courses | |
| Recommended Elective Courses |
| Language of Course | English |
| Course Level | First Cycle (Bachelor's Degree) |
| Course Type | Elective |
| Course Coordinator | Assist.Prof. Mustafa AKTAN |
| Name of Lecturer(s) | Assist.Prof. Mustafa AKTAN |
| Assistant(s) | |
| Aim | Mastering the hardware description language, Verilog HDL, for the design (specification, simulation, and synthesis) of digital systems and implementing them on FPGAs. |
| Course Content | This course contains; Digital Systems Review,FPGA Systems,Digital System Modelling using Verilog,Verilog Modelling Styles: Structural,Verilog Modelling Styles: Dataflow,Verilog Modelling Styles: Behavioral,Design verification,Combinational circuit design using Verilog,Sequential circuit design using Verilog,Finite State Machine Design using Verilog,CPU Design,Synthesis,Implementation of Verilog design on FPGA,Design Optimization. |
| Dersin Öğrenme Kazanımları | Teaching Methods | Assessment Methods |
| Structural, dataflow, and behavioral Modelling of digital blocks using Verilog HDL | 10, 12, 14, 16, 17, 19, 2, 21, 5, 6, 9 | A, E, F |
| Modelling, simulating, and testing combinational circuits in Verilog | 10, 12, 14, 16, 17, 19, 2, 21, 5, 6, 9 | A, E, F |
| Modelling, simulating, and testing sequential circuits in Verilog | 10, 12, 14, 16, 17, 19, 2, 21, 5, 6, 9 | A, E, F |
| Digital System Synthesis for FPGA | 10, 12, 14, 16, 17, 19, 2, 21, 5, 6, 9 | A, E, F |
| Digital System Optimization for FPGA | 10, 12, 14, 16, 17, 19, 2, 21, 5, 6, 9 | A, E, F |
| Teaching Methods: | 10: Discussion Method, 12: Problem Solving Method, 14: Self Study Method, 16: Question - Answer Technique, 17: Experimental Technique, 19: Brainstorming Technique, 2: Project Based Learning Model, 21: Simulation Technique, 5: Cooperative Learning, 6: Experiential Learning, 9: Lecture Method |
| Assessment Methods: | A: Traditional Written Exam, E: Homework, F: Project Task |
Course Outline
| Order | Subjects | Preliminary Work |
|---|---|---|
| 1 | Digital Systems Review | Read the book |
| 2 | FPGA Systems | Read the book |
| 3 | Digital System Modelling using Verilog | Read the book |
| 4 | Verilog Modelling Styles: Structural | Read the book |
| 5 | Verilog Modelling Styles: Dataflow | Read the book |
| 6 | Verilog Modelling Styles: Behavioral | Read the book |
| 7 | Design verification | Read the book |
| 8 | Combinational circuit design using Verilog | Read the book |
| 9 | Sequential circuit design using Verilog | Read the book |
| 10 | Finite State Machine Design using Verilog | Read the book |
| 11 | CPU Design | Read the book |
| 12 | Synthesis | Read the book |
| 13 | Implementation of Verilog design on FPGA | Read the book |
| 14 | Design Optimization | Read the book |
| Resources |
| Mano, Ciletti: Digital Design with an Introduction to the Verilog HDL, VHDL, and System Verilog, 6E Thomas, Moorby: The Verilog Hardware Description Language |
Course Contribution to Program Qualifications
| Course Contribution to Program Qualifications | |||||||
| No | Program Qualification | Contribution Level | |||||
| 1 | 2 | 3 | 4 | 5 | |||
| 1 | 1. An ability to apply knowledge of mathematics, science, and engineering | X | |||||
| 2 | 2. An ability to identify, formulate, and solve engineering problems | X | |||||
| 3 | 3. An ability to design a system, component, or process to meet desired needs within realistic constraints such as economic, environmental, social, political, ethical, health and safety, manufacturability, and sustainability | X | |||||
| 4 | 4. An ability to use the techniques, skills, and modern engineering tools necessary for engineering practice | X | |||||
| 5 | 5. An ability to design and conduct experiments, as well as to analyze and interpret data | X | |||||
| 6 | 6. An ability to function on multidisciplinary teams | X | |||||
| 7 | 7. An ability to communicate effectively | X | |||||
| 8 | 8. A recognition of the need for, and an ability to engage in life-long learning | X | |||||
| 9 | 9. An understanding of professional and ethical responsibility | X | |||||
| 10 | 10. A knowledge of contemporary issues | X | |||||
| 11 | 11. The broad education necessary to understand the impact of engineering solutions in a global, economic, environmental, and societal context | X | |||||
Assessment Methods
| Contribution Level | Absolute Evaluation | |
| Rate of Midterm Exam to Success | 30 | |
| Rate of Final Exam to Success | 70 | |
| Total | 100 | |
| ECTS / Workload Table | ||||||
| Activities | Number of | Duration(Hour) | Total Workload(Hour) | |||
| Course Hours | 14 | 3 | 42 | |||
| Guided Problem Solving | 0 | 0 | 0 | |||
| Resolution of Homework Problems and Submission as a Report | 5 | 12 | 60 | |||
| Term Project | 14 | 5 | 70 | |||
| Presentation of Project / Seminar | 0 | 0 | 0 | |||
| Quiz | 0 | 0 | 0 | |||
| Midterm Exam | 1 | 32 | 32 | |||
| General Exam | 1 | 40 | 40 | |||
| Performance Task, Maintenance Plan | 0 | 0 | 0 | |||
| Total Workload(Hour) | 244 | |||||
| Dersin AKTS Kredisi = Toplam İş Yükü (Saat)/30*=(244/30) | 8 | |||||
| ECTS of the course: 30 hours of work is counted as 1 ECTS credit. | ||||||
Detail Informations of the Course
Course Description
| Course | Code | Semester | T+P (Hour) | Credit | ECTS |
|---|---|---|---|---|---|
| EMBEDDED SYSTEMS | - | Spring Semester | 3+2 | 4 | 8 |
| Course Program |
| Prerequisites Courses | |
| Recommended Elective Courses |
| Language of Course | English |
| Course Level | First Cycle (Bachelor's Degree) |
| Course Type | Elective |
| Course Coordinator | Assist.Prof. Mustafa AKTAN |
| Name of Lecturer(s) | Assist.Prof. Mustafa AKTAN |
| Assistant(s) | |
| Aim | Mastering the hardware description language, Verilog HDL, for the design (specification, simulation, and synthesis) of digital systems and implementing them on FPGAs. |
| Course Content | This course contains; Digital Systems Review,FPGA Systems,Digital System Modelling using Verilog,Verilog Modelling Styles: Structural,Verilog Modelling Styles: Dataflow,Verilog Modelling Styles: Behavioral,Design verification,Combinational circuit design using Verilog,Sequential circuit design using Verilog,Finite State Machine Design using Verilog,CPU Design,Synthesis,Implementation of Verilog design on FPGA,Design Optimization. |
| Dersin Öğrenme Kazanımları | Teaching Methods | Assessment Methods |
| Structural, dataflow, and behavioral Modelling of digital blocks using Verilog HDL | 10, 12, 14, 16, 17, 19, 2, 21, 5, 6, 9 | A, E, F |
| Modelling, simulating, and testing combinational circuits in Verilog | 10, 12, 14, 16, 17, 19, 2, 21, 5, 6, 9 | A, E, F |
| Modelling, simulating, and testing sequential circuits in Verilog | 10, 12, 14, 16, 17, 19, 2, 21, 5, 6, 9 | A, E, F |
| Digital System Synthesis for FPGA | 10, 12, 14, 16, 17, 19, 2, 21, 5, 6, 9 | A, E, F |
| Digital System Optimization for FPGA | 10, 12, 14, 16, 17, 19, 2, 21, 5, 6, 9 | A, E, F |
| Teaching Methods: | 10: Discussion Method, 12: Problem Solving Method, 14: Self Study Method, 16: Question - Answer Technique, 17: Experimental Technique, 19: Brainstorming Technique, 2: Project Based Learning Model, 21: Simulation Technique, 5: Cooperative Learning, 6: Experiential Learning, 9: Lecture Method |
| Assessment Methods: | A: Traditional Written Exam, E: Homework, F: Project Task |
Course Outline
| Order | Subjects | Preliminary Work |
|---|---|---|
| 1 | Digital Systems Review | Read the book |
| 2 | FPGA Systems | Read the book |
| 3 | Digital System Modelling using Verilog | Read the book |
| 4 | Verilog Modelling Styles: Structural | Read the book |
| 5 | Verilog Modelling Styles: Dataflow | Read the book |
| 6 | Verilog Modelling Styles: Behavioral | Read the book |
| 7 | Design verification | Read the book |
| 8 | Combinational circuit design using Verilog | Read the book |
| 9 | Sequential circuit design using Verilog | Read the book |
| 10 | Finite State Machine Design using Verilog | Read the book |
| 11 | CPU Design | Read the book |
| 12 | Synthesis | Read the book |
| 13 | Implementation of Verilog design on FPGA | Read the book |
| 14 | Design Optimization | Read the book |
| Resources |
| Mano, Ciletti: Digital Design with an Introduction to the Verilog HDL, VHDL, and System Verilog, 6E Thomas, Moorby: The Verilog Hardware Description Language |
Course Contribution to Program Qualifications
| Course Contribution to Program Qualifications | |||||||
| No | Program Qualification | Contribution Level | |||||
| 1 | 2 | 3 | 4 | 5 | |||
| 1 | 1. An ability to apply knowledge of mathematics, science, and engineering | X | |||||
| 2 | 2. An ability to identify, formulate, and solve engineering problems | X | |||||
| 3 | 3. An ability to design a system, component, or process to meet desired needs within realistic constraints such as economic, environmental, social, political, ethical, health and safety, manufacturability, and sustainability | X | |||||
| 4 | 4. An ability to use the techniques, skills, and modern engineering tools necessary for engineering practice | X | |||||
| 5 | 5. An ability to design and conduct experiments, as well as to analyze and interpret data | X | |||||
| 6 | 6. An ability to function on multidisciplinary teams | X | |||||
| 7 | 7. An ability to communicate effectively | X | |||||
| 8 | 8. A recognition of the need for, and an ability to engage in life-long learning | X | |||||
| 9 | 9. An understanding of professional and ethical responsibility | X | |||||
| 10 | 10. A knowledge of contemporary issues | X | |||||
| 11 | 11. The broad education necessary to understand the impact of engineering solutions in a global, economic, environmental, and societal context | X | |||||
Assessment Methods
| Contribution Level | Absolute Evaluation | |
| Rate of Midterm Exam to Success | 30 | |
| Rate of Final Exam to Success | 70 | |
| Total | 100 | |